1. Field of the Invention
The present invention relates to a method for testing a semiconductor device, which is suitable for testing a semiconductor device equipped with a memory capable of reading and writing at high speed, and an apparatus for testing a semiconductor device that operates using the testing method.
2. Related Art
The brief summary of an apparatus for testing a semiconductor device to test a general semiconductor device will be described for confirmation before the prior art relating to the present invention is described. FIG. 25 shows a configuration of a conventional apparatus for testing a semiconductor device. TES in FIG. 25 represents the overall apparatus for testing a semiconductor device. The apparatus for testing a semiconductor device TES consists of a main controller 13, a pattern generator 14, a timing generator 15, a waveform formatter 16, a logic comparator 12, a driver 17, a signal reading circuit 11, a bad analysis memory 18, a logical amplitude reference voltage source 19, a comparison reference voltage source 21 and a device source 22 etc.
The main controller 13, which is generally configured by a computer system, mainly controls the pattern generator 14 and the timing generator 15 in accordance with a test program prepared by a user, allows the pattern generator 14 to generate the test pattern data, changes the test pattern data into the test pattern signals having actual waveforms with the waveform formatter 16 and applies the test pattern signals to a semiconductor device to be tested DUT in order to store it via the driver 17 which amplifies the voltages of the waveforms having amplitude values set by the logical amplitude reference voltage source 19.
The signal reading circuit 11 reads out logical values from the response signals read from the semiconductor device to be tested DUT. The logic comparator 12 compares the logical values read out by the signal reading circuit 11 with the expected values outputted by the pattern generator 14, judges that there is a defect in the memory cell of the address when a non-coincidence occurs, stores the fail address into the bad analysis memory 18 for every fail occurrence, and judges, for example, whether the fail cell can be repaired after the test.
Although FIG. 25 shows a configuration of the test apparatus for one pin, practically, this configuration is provided for a plurality of pins of the semiconductor device to be tested DUT, and the input of the test patterns and the reading of the response signals from the semiconductor device to be tested DUT are conducted for every pin. These are the configurations of the apparatus for testing a semiconductor device for the general semiconductor device.
Meanwhile, in the semiconductor device such as a memory configured with a semiconductor device, there is a memory which performs data passing by using the timing of the clock, writing data into the semiconductor device synchronized with the clock by inputting the data together with the clock, while retrieving the data from the semiconductor device synchronized with the clock together with the clock.
FIG. 26 shows a state of reading of this kind of memory. DA, DB, DC . . . in FIG. 26A represent the data outputted by the semiconductor device (the data outputted from one of the pins). DQS shown in FIG. 26B the clock outputted from the memory. The data DA, DB, DC . . . is outputted from the semiconductor device synchronized with the clock DQS. This clock is used as a synchronization signal (data strobe) when passing the data DA, DB, DC . . . to other circuits.
As a test item when testing this kind of semiconductor device, there is an item to measure a time difference (phase difference) dI1, dI2, dI3 . . . from the timing at rising or falling of each of the clocks DQS (hereinafter, the clock is referred to as reference clock) to the transition point of the data. As the time difference dI1, dI2, dI3 . . . is short as possible it is evaluated as a device having an excellent characteristic that the response is fast. The grade of the semiconductor device to be tested is decided by the length of the time difference.
In regard to the reference clock DQS outputted from the semiconductor device to be tested, the clock generated by the clock source in applied to the semiconductor device, the clock is distributed to the circuits in the semiconductor device, and the data is outputted synchronized with the clock. Therefore, even when performing test with the apparatus for testing a semiconductor device, the clock from the apparatus for testing a semiconductor device is applied to the semiconductor device to be tested, the clock is outputted with the data as the reference clock for data delivery through the inside of the semiconductor device to be tested. Accordingly, the timing of rising or falling of the reference clock is measured and the time dI1, dI2, dI3 . . . from the timing of rising or falling measured to the transition point of the data DA, DB, DC . . . is measured.
As described above, since the reference clock outputted from the semiconductor device is outputted through the inside of the semiconductor device, the timing of rising and the timing of falling is considerably affected by the inside of the semiconductor device and the external environment such as temperature, so we can find a phenomenon that differences between the phases of the reference clocks DQS1, DQS2, DQS3 . . . occur for every semiconductor device as shown in FIG. 27. Further, added to that the phase difference is caused by the difference of each semiconductor device, we can find a phenomenon that jitter occurs, where in the phase difference is changed by the difference of the address of the memory accessed and the time transition (thermal change) even in the semiconductor device.
Therefore, in order to exactly measure the time dI1, dI2, dI3 . . . from the timing of rising or the timing of falling of the reference clock DQS to the transition point of the data DA, DB, DC . . . , it is necessary to exactly measure the timing of rising or the timing of falling of the reference clock DQS outputted from the semiconductor device in advance. Accordingly, the prior art gradually shifts the timing of applying the strobe of a signal reading circuit, with which the apparatus for testing a semiconductor device is equipped, measures the timing of rising or falling of the reference clock DQS, and measures the time dI1, dI2, dI3 . . . using the measurement result.
FIG. 28 shows a part for measuring the timing of rising or falling of the reference clock DQS being used in the prior art. The level comparator 10 is configured with a pair of voltage comparators CP1 and CP2, and judges whether or not the logical value of the reference clock DQS outputted by the semiconductor device to be tested DUT satisfies the normal voltage condition by a pair of voltage comparators CP1 and CP2. The voltage comparator CP1 judges whether or not the voltage value of the H logic of the reference clock DQS is more than the normal voltage value VOH. The voltage comparator CP2 judges whether or not the voltage value of the L logic of the reference clock DQS is less than the normal voltage value VOL.
These judgment results are inputted into the signal reading circuit 11, and the signal reading circuit 11 measures the timing of rising or the timing of falling of the reference clock DQS. The signal reading circuit 11 reads the logical value inputted at every timing of applying the strobe STB.
FIG. 29 shows an example of phases of the strobes in regard to DQS. The strobes STB are applied while being given phase differences (τT) by a small amount for each test cycle as shown in FIG. 29. That is, the strobes STB are given to the signal reading circuit 11 by one for each test cycle, and the state of the output of the voltage comparators CP1 and CP2 is read.
The logic comparator 12 compares the logical value outputted by the signal reading circuit 11 and the expected value, which is predetermined (the H logic as an example in FIG. 28), and outputs the pass signal PA, which indicates a pass (good), if the logical value outputted by the signal reading circuit 11 coincides with the expected value. The timing of the rising of the reference clock DQS is decided by obtaining the time T1 (FIG. 29C) from the occurrence timing of the strobe STB1 (FIG. 29B) when the output of the level comparator 10 is read to be reversed in the H logic (the occurrence timing of the strobes STB has already been known).
In case of detecting the timing of falling of the reference clock DQS, the timing of falling is detected by the strobe when the output of the voltage comparator CP2 is read to be reversed in the H logic like the detection of rising, while the strobe STB occurs at a timing after the timing of rising of the reference clock DQS in the H logic.
As described above, since the prior art measures the occurrence timing of the reference clock DQS by the timing measurement method using the signal reading circuit 11, with which the apparatus for testing a semiconductor device is equipped, and the strobe STB, which is applied to the signal reading circuit 11, there is a defect that it takes time to necessarily perform the test cycle TD many times repeatedly even when measuring only the timing of rising or falling of the reference clock DQS.
Furthermore, since the method of measuring the timing of rising or falling of the reference clock DQS have to measure all of the addresses of the memory to be tested or to measure all the way from the start to the end of the test pattern in case of avoiding the influence of the jitter caused by the heat, it is necessary to take long time to measure the timing of rising or falling of the reference clock. Although it is considered that the phase difference τT, which is given to the strobe STB, is adopted roughly so as to reduce the number of times of performing the test cycle as a method of decreasing the time taken in measuring the timing of rising or falling of the reference clock DQS, there is a defect that the reliability of the measurement result of the time dI1, dI2, dI3 . . . until the transition point the reference clock DQS and the data DA, DB, DC . . . is decreased because the accuracy of measuring the timing of rising or falling of the reference clock DQS is decreased if the phase difference τT, which is given to the strobe STB, is changed roughly.